This application claims priority to Korean Patent Application 2002-10539, filed on Feb. 27, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor integrated circuit (IC) devices and methods for manufacturing the same, and more particularly, to semiconductor devices having multilevel interconnections and methods for manufacturing the same.
As the density and integration of semiconductor devices increases, the number of multilevel metal interconnections generally increases. It is generally desirable that metal interconnections are economical to fabricate while having low electrical resistance and high reliability. To satisfy these requirements, aluminum (Al) is widely used for metal interconnections.
As the critical dimensions of the circuit become smaller, technical limits in applying a conventional technique to a deposition process for forming Al interconnections when manufacturing a semiconductor device can be approached. In forming a via contact stud for electrically connecting the Al interconnection on a lower layer with the Al interconnection on an upper layer, it is desirable to form the via contact stud such that it provides a low contact resistance as well as completely filling the inside of a via hole with an interconnection material. Various processes have been developed to obtain desired electrical and filling characteristics in forming via contact plugs for multilevel interconnections.
FIGS. 1 and 2 are sectional views depicting a conventional method for manufacturing a semiconductor device having multilevel interconnections. Referring to FIGS. 1 and 2, a lower metal interconnection layer including an Al layer 4 and a capping layer 5 is formed on a semiconductor substrate 2 having predetermined circuit patterns (not shown) and insulating layer (not shown) thereon. In the illustrated case, the capping layer 5 is formed of a titanium (Ti) layer 5a and titanium nitride (TiN) layer 5b. An intermetal dielectric layer 6 having a via hole 6a, which exposes a portion of the capping layer 5, is formed on the lower metal interconnection layer. A glue layer 7 formed of Ti and a TiN barrier layer 8 are successively formed in the hole 6a. In order to form multilevel interconnections having a feature size corresponding to a submicron design rule, the width of the via hole 6a is reduced to less than 250 nm, so that aspect ratio is increased. Consequently, the step coverage of the TiN barrier layer 8 may be reduced in the via hole 6a, lowering the thickness of the TiN barrier layer 8 in the via hole 6a, such that and TiN barrier layer 8 may not properly serve as a barrier.
In order to complete a via contact stud and an upper metal interconnection layer 9 as shown in FIG. 2, an Al layer is deposited on the resultant structure by a sputtering process. The Al layer is reflowed by a thermal process to fill the inside of the via hole 6a with the interconnection material. As a result, the Ti in the glue layer 7 and the Al in the Al layer may react to form uneven titanium/aluminum alloy (TiAlx) layers 7a and 9a in the via hole 6a. 
When uneven TiAlx layers like the layers 7a and 9a are formed on the via contact studs in a wafer, the contacts in a wafer may have a uneven profile. Accordingly, the resistance distributions of the contacts may be undesirable, and the resistance characteristic may be further degraded after the thermal process. Moreover, a high resistance material, such as aluminum nitride (AlN), may be formed by reaction between the TiN barrier layer 8 and the Al layer thereon, so that a further increase in the contact resistance and deterioration of reliability may occur.
FIGS. 3 and 4 are graphs illustrating resistance distributions via contact studs in a conventional semiconductor device as described above. FIG. 3 illustrates the result of the contact resistance distribution of the via contact studs shown in FIG. 2 according to the size of the via contact studs, before the thermal process is performed. FIG. 4 illustrates the result of the contact resistance distribution of the via contact stud shown in FIG. 2, after a hot temperature storage (HTS) reliability test in which the thermal process is performed at a temperature of 350xc2x0 C. for 100 hours in a nitrogen atmosphere.
As shown in FIGS. 3 and 4, the resistance of the via contact stud in the conventional semiconductor device is about 8 xcexa9 for each contact while the resistance distribution is plus or minus 5 xcexa9, before the thermal process. However, as shown in FIG. 4, after the thermal process at a temperature of 350xc2x0 C. for 100 hours, the contact resistance can deteriorate to tens and thousands of xcexa9, with a greater resistance distribution.
Accordingly, as the width of the contact size is reduced to less than 250 nm in the via contact stud structures of the conventional semiconductor device, contacts may have uneven profiles caused by the high resistance material, such as the AlN which is formed by the reaction between a TiN barrier layer and an Al layer, and by unevenness in the TiAlx layer. Contact resistance may increase while deteriorating the resistance distribution, so that reliability of the device may be degraded.
According to some embodiments of the present invention, a semiconductor device includes a first metal interconnection layer on a semiconductor substrate, an intermetal dielectric layer on the first metal interconnection layer, and a second metal interconnection layer on the intermetal dielectric layer. A contact stud electrically connects the first and second metal interconnection layers through the intermetal dielectric layer, and includes a titanium/aluminum (TiAlx) core extending from the first metal interconnection layer toward the second metal interconnection layer.
The contact stud may further include a TiAlx liner disposed on bottom and sidewalls of the TiAlx core and a titanium nitride (TiN) barrier layer interposed between the TiAlx core and the TiAlx liner. The first metal interconnection layer and/or the second metal interconnection layer may include Al. For example, the first metal interconnection layer may include an aluminum-containing layer and a reflection barrier capping layer on the aluminum-containing layer. The reflection barrier capping layer may include a titanium (Ti) layer on the aluminum-containing layer and a titanium nitride (TiN) layer on the Ti layer. The intermetal dielectric layer may include a first tetraethylorthosilicate (P-TEOS) layer on the first metal interconnection layer, a flowable oxide (FOX) layer on the first P-TEOS layer, and a second P-TEOS layer on the FOX layer.
According to method embodiments of the invention, a contact stud in a semiconductor device is fabricated. A portion of an insulating layer of a semiconductor substrate is removed to form a hole that exposes an underlying conductive layer. A glue layer is formed on bottom and sidewalls of the hole. A Ti seed layer is formed on the glue layer in the hole. An aluminum-containing layer is formed on the Ti seed layer. The substrate is thermally treated to form a contact stud that extends through the hole in the insulating layer to electrically contact the underlying conductive layer, the contact stud including a TiAlx core. A TiN barrier layer may be formed on the glue layer in the hole before forming the Ti seed layer. The thermal treating may include maintaining the substrate at a temperature of about 350xc2x0 C. to about 550xc2x0 C. Thermal treatment may reflow the aluminum-containing layer and react aluminum in the reflowed aluminum-containing layer with titanium in the Ti seed layer to form the TiAlx core.